Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data in most areas of business, science, education and entertainment. The manner in which the electronic devices perform operations can have a significant impact on performance and end results and testing device performance is often important. However, conventional approaches to testing component operations can have many limitations and can be very complex and complicated.
Traditional scan flip flops are used in many kinds of integrated circuits for various testing purposes (e.g., in order to test chips for defects). The traditional approaches often use inputs derived by automatic test pattern generation (ATPG). Both tester time and test escapes which are packaged and later discarded present a significant cost to integrated circuit manufacturers. Some traditional approaches attempt to mitigate this by adding test features to chips to enable quick and reliable testing. In a modern processor, that often means that a majority of flip flops have scan features, which typically allows ATPG patterns to be shifted in from flip-flop to flip-flop in order to provide inputs for test and then captured test results to be shifted out for comparison with expected values. In some conventional mux-scan methods, scan testing utilizes a scan mux in the flip flop, which typically selects either between data input in functional mode or scan input in scan shift mode, based on a scan enable signal acting as a select. FIG. 1A is a block diagram of a prior art scan latch system, including selectors 110 and 120 and control component 130. FIG. 1 B is an illustration of a prior art scan master slave flip flop approach utilizing the master latch system of FIG. 1A. FIG. 2A is a block diagram of another prior art scan latch system with gated clock, including selector 220 and control component 230. FIG. 2B is an illustration of another prior art scan master slave flip flop approach utilizing the master latch system of FIG. 2A.
In recent years there has been an increased focus on power consumption and some conventional approaches try to reduce the usage of high power fast dynamic and sense amplifier flip flops in favor of static flip flops. However, static master slave flip flops are usually slower than dynamic topologies and there has been increased focus on improving the speed of static flip flops so they can better serve as replacements to dynamic and sense amplifier flip flops in critical paths. In some prior art designs, the select to the scan mux are gated by a clock (e.g., to take the clocked transmission gate out of the critical path) in an attempt to improve speed. In those prior art designs, the scan multiplexor is still put in the critical data path of the flip flop, which adds extra diffusion and parasitic loads to the critical path, typically resulting in additional delay overhead for the flip flop, even when the flip flop is not used for scan.